Nextest Magnum EV Test System *used working - Tech Equipment Spares, LLC

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Nextest Magnum EV Test System *used working

Name: Nextest Magnum EV Test System *used working
Brand: Nextest
SKU: 29-3001
Price: 60000.00 USD
Availability: OutOfStock

NextestSKU: 29-3001

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Nextest Magnum EV Test System *used working

Inventory# 29-3001

This Nextest Magnum EV Test System, is used working surplus. The physical condition of the unit is good and clean. Note, the carts in the picture are not included.

Note, if more pictures are needed, please contact us.

Also, buyer has the option to use their own shipping account. If buyer chooses to use their shipping account, please contact us to remove the shipping cost from invoice after order is placed.

Specifications

Model#: Magnum EV
1280 channels cable ready
2 site boards (256 pin electronics channels)
2 site DPO64 option boards
Per site : 128 PE channels, 8PMU, 8DPS, 16 high voltage source 8DC test measurements, 16/32 SDR/DDR LVM, 1152Mbits DBM, 1152 MBits ECR1 1152 MBits ECR2

System Diagnostic Report (below):

HSB1 SERIAL# 986446

Creating HOB object in slot 5

HOB5 SERIAL# 192700

Loaded VCAL Data on hob5 from CALMOD (Last Cal:5/18/2011 01:07:50 UTC)

Creating module object type:t_dpo_module, instance:1, HOB slot:5, location:1

DPO1 SERIAL# 170925, inst:1, type:1 (DPO_V2)

Loaded VCAL Data on dpo1 (Last Cal:8/20/2021 17:12:38 UTC)

Creating module object type:t_dpo_module, instance:2, HOB slot:5, location:2

DPO2 SERIAL# 170949, inst:2, type:1 (DPO_V2)

Loaded VCAL Data on dpo2 (Last Cal:8/20/2021 17:12:40 UTC)

Creating module object type:t_dpo_module, instance:3, HOB slot:5, location:3

DPO3 SERIAL# 170863, inst:3, type:1 (DPO_V2)

Loaded VCAL Data on dpo3 (Last Cal:8/20/2021 17:12:42 UTC)

Creating module object type:t_dpo_module, instance:4, HOB slot:5, location:4

DPO4 SERIAL# 170931, inst:4, type:1 (DPO_V2)

Loaded VCAL Data on dpo4 (Last Cal:8/20/2021 17:12:44 UTC)

Creating module object type:t_dpo_module, instance:5, HOB slot:5, location:5

DPO5 SERIAL# 170881, inst:5, type:1 (DPO_V2)

Loaded VCAL Data on dpo5 (Last Cal:8/20/2021 17:12:46 UTC)

Creating module object type:t_dpo_module, instance:6, HOB slot:5, location:6

DPO6 SERIAL# 160060, inst:6, type:1 (DPO_V2)

Loaded VCAL Data on dpo6 (Last Cal:8/20/2021 17:12:49 UTC)

Creating module object type:t_dpo_module, instance:7, HOB slot:5, location:7

DPO7 SERIAL# 170936, inst:7, type:1 (DPO_V2)

Loaded VCAL Data on dpo7 (Last Cal:8/20/2021 17:12:51 UTC)

Creating module object type:t_dpo_module, instance:8, HOB slot:5, location:8

DPO8 SERIAL# 170916, inst:8, type:1 (DPO_V2)

Loaded VCAL Data on dpo8 (Last Cal:8/20/2021 17:12:53 UTC)

Test Program Y:\nextest\h3.10.7c\bin\systemdiag.exe

Loading VCAL Data on t_hsb1, t_pe32_1

Loading VCAL Data on t_hsb1, t_pe32_2

Loading VCAL Data on t_hsb1, t_pe32_3

Loading VCAL Data on t_hsb1, t_pe32_4

Loading VCAL Data on t_hsb1, t_dps_pmu_1

Loading VCAL Data on t_hsb1, t_dps_pmu_2

Loading VCAL Data on t_hsb1, t_dps_pmu_3

Loading VCAL Data on t_hsb1, t_dps_pmu_4

Loading TCAL Data on t_hsb1, t_pe32_1

Loading TCAL Data on t_hsb1, t_pe32_2

Loading TCAL Data on t_hsb1, t_pe32_3

Loading TCAL Data on t_hsb1, t_pe32_4

Loading TCal TDR data from DUT board EEPROM

Creating pattern set => Logic_set

Creating pattern set => PE32_ps_ddr_set

Creating pattern set => PE32_ps_set

Creating pattern set => PE32_tg_set

Creating pattern set => default_set

The test program is loaded

HostName: NEXTEST846887

Nextest software release: c:\nextest\h3.10.7c

chassis 1 SET DB_DIAGCMD=1 -> success

TestStarted(1)...

Started: 08/21/21 14:18:19

Current Time is: 08/21/21 14:18:31

- Site controller details -

Intel(R) Pentium(R) III CPU - S 1266MHz, 497MB total physical memory.

Microsoft Windows XP

2600.xpsp2.030422-1633

- Revision Codes for Boards -

*** Summary of board set for SA pn: 508540 ***

*** Summary of option board set for HOB5 Assembly pn: 508586 ***

Site 1 ( Chassis 1, Slot 1 )

Board Serial PWB PWB PWA PWA LVM DBM ECR1 ECR2 X Y D

Name Number Number Rev Number Rev SDR/DDR MBits MBits MBits bits bits bits

-----------------------------------------------------------------------------------------------------------

HSBX 986446 503539 2 507487 10 16/32 (2) 1152(2) 1152(2) 1152(2) 18* 16* 36*

PEXL_1 987396 507834 1 507835 5

PEXL_2 986186 507834 1 507835 5

PEXL_3 994503 507834 1 507835 5

PEXL_4 987202 507834 1 507835 5

DPX20_1 985083 504582 9 508488 4

DPX20_2 988595 504582 9 508488 4

DPX20_3 997300 504582 9 508488 4

DPX20_4 988313 504582 9 508488 4

IPC 166504 505306 5 505305 24 Firmware Revision : 3.8.4

HOB_5 192700 509988 1 509989 7

DPO_1 170925 507610 2 507611 9

DPC_1 180839 513555 2 513554 2

DPO_2 170949 507610 2 507611 9

DPC_2 180814 513555 2 513554 2

DPO_3 170863 507610 2 507611 9

DPC_3 193047 513555 2 513554 2

DPO_4 170931 507610 2 507611 9

DPC_4 180929 513555 2 513554 2

DPO_5 170881 507610 2 507611 9

DPC_5 193350 513555 2 513554 2

DPO_6 160060 507610 2 507611 9

DPC_6 180763 513555 2 513554 2

DPO_7 170936 507610 2 507611 9

DPC_7 180863 513555 2 513554 2

DPO_8 170916 507610 2 507611 9

DPC_8 193214 513555 2 513554 2

* NOTE: The ECR X, Y, D bits represent the maximum allowable configuration.

* NOTE: This tester is properly configured to support the 300mA/600mA DPS option.

- Revision Codes for Memory Modules -

Module Base PWA PWA LVM DBM ECR

Name Number Number Rev MVec MBits MBits

-------------------------------------------------------------------

DBM-DIMM1 505480 505943 1 576

DBM-DIMM2 505480 505943 1 576

ECR1-DIMM1 505480 505937 1 576

ECR1-DIMM2 505480 505937 1 576

ECR2-DIMM1 505480 505937 1 576

ECR2-DIMM2 505480 505937 1 576

LVM1-DIMM1 505480 505949 1 16

LVM2-DIMM1 505480 505949 1 16

- Revision Codes for FPGAs -

FPGA SW HW

Name Rev Rev

-------------------------

CPUI Fpga 0x1 0x9

TG1 Fpga 0x1 0x18

TG2 Fpga 0x1 0x18

TG3 Fpga 0x1 0x18

TG4 Fpga 0x1 0x18

TG5 Fpga 0x1 0x18

TG6 Fpga 0x1 0x18

TG7 Fpga 0x1 0x18

TG8 Fpga 0x1 0x18

APG1 Fpga 0x1 0xf3

APG2 Fpga 0x1 0xb0

DBM1 Fpga 0x1 0xbf

PSLE1 Fpga 0x1 0x88

PSS1 Fpga 0x1 0x90

PSLE2 Fpga 0x1 0x88

PSS2 Fpga 0x1 0x90

PSLE3 Fpga 0x1 0x88

PSS3 Fpga 0x1 0x90

PSLE4 Fpga 0x1 0x88

PSS4 Fpga 0x1 0x90

LVM1 Fpga 0x1 0x4e

LVM2 Fpga 0x1 0x4f

ECR1 Fpga 0x1 0xca

ECR2 Fpga 0x1 0xca

HOB_5 Fpga 0x1 0xe

DPO_1 Fpga 0x1 0x17

DPO_2 Fpga 0x1 0x17

DPO_3 Fpga 0x1 0x17

DPO_4 Fpga 0x1 0x17

DPO_5 Fpga 0x1 0x17

DPO_6 Fpga 0x1 0x17

DPO_7 Fpga 0x1 0x17

DPO_8 Fpga 0x1 0x17

Nextest software release: C:\nextest\h3.10.7C\Bin\Ui.exe

Running on MAGNUM_X20 system# 846887

HOST computer name: NEXTEST846887

N3VBB: -3.913

Testing APG read,write registers via cpu [apg_rw_regs_tb]

Testing Address registers and LBDATA

Testing MAR and INTA

Testing JAM, DMAIN, DBASE, YINDEX

Testing Unique values

Testing APG counter RAM - short march [apg_counter_ram_short_march_tb]

Testing APG reload RAM - short march [apg_reload_ram_short_march_tb]

Testing APG XDTOPO RAM - short march [apg_xdtopo_ram_short_march_tb]

Testing APG YDTOPO RAM - short march [apg_ydtopo_ram_short_march_tb]

Testing APG uRAM - short march [apg_uram_ram_short_march_tb]

Testing APG Cycle Length RAM - short march [apg_cycle_ram_short_march_tb]

Testing APG DAC RAM - short march [apg_dac_ram_short_march_tb]

Testing APG XTOPO RAM - short march [apg_xtopo_ram_short_march_tb]

Testing APG YTOPO RAM - short march [apg_ytopo_ram_short_march_tb]

Testing APG User RAM - short march [apg_user_ram_short_march_tb]

Testing APG vRAM - short march [apg_vram_ram_short_march_tb]

Testing APG vRAM VMC1 DIMM1 - Bit Independence Test

Testing APG vRAM VMC1 DIMM1 - Address Independence Test

Setting up background data

Test and write complement with ascending address

Test and write complement with descending address

Setting up background data

Test and write complement with ascending address

Test and write complement with descending address

Testing APG vRAM VMC2 DIMM1 - Bit Independence Test

Testing APG vRAM VMC2 DIMM1 - Address Independence Test

Setting up background data

Test and write complement with ascending address

Test and write complement with descending address

Setting up background data

Test and write complement with ascending address

Test and write complement with descending address

Testing HSB 100Mhz clock frequency [hsb_clk_check_tb]

Testing APG counter functions [apg_counter_tests_tb]

Pattern start is at 4de

Testing Counter loading

Testing Counter address

Testing Reload loading

Testing Reload address

Testing Reload counters from reload registers

Testing Counter DECR

Testing Counter INCR

Testing Counter DECR2

Testing MAR increments, stack nesting [apg_mar_and_stack_tests_tb]

Testing MAR increments

Testing Stack nesting, 1st pass

Testing Stack nesting, 2nd pass

Stack nesting, 50nS

Stack nesting, 20nS

Testing APG counter branching [apg_counter_branching_tb]

Pattern start is at 61a

Testing APG timer branching and accuracy [apg_timer_branching_tb]

Pattern start is at bd

Testing APG interrupt branch logic and addressing [apg_interrupt_branching_tb]

Pattern start is at 718

Testing APG address generators [apg_address_generators_tb]

Pattern start is at 629

Testing uDATA loads

Testing COMP function

Testing logic functions

Testing add

Testing subtract

Testing decrement and increment

Testing Y to X carries and borrows

Testing X to Y carries and borrows

Testing APG data generator [apg_data_generator_tb]

Pattern start is at 69

Testing uDATA loads

Testing Count up and down with shift left, 18 bit DMAIN register

Testing Count up and down with shift left, 18 bit DBASE register

Testing Shift right, 18 bit DMAIN register

Testing Shift right, 18 bit DBASE register

Testing Rotate left, 18 bit DMAIN register

Testing Rotate right, 18 bit DMAIN register

Testing Rotate left, 18 bit DBASE register

Testing Rotate right, 18 bit DBASE register

Testing Rotate left, 36 bit DMAIN register

Testing Rotate right, 36 bit DMAIN register

Testing Rotate left, 36 bit DBASE register

Testing Rotate right, 36 bit DBASE register

Testing Shift left, 36 bit DMAIN register

Testing Shift left, 36 bit DBASE register

Testing Shift right, 36 bit DMAIN register

Testing Shift right, 36 bit register

Testing APG error pipelines [apg_error_pipe_tb]

Testing APG data inversions [apg_data_inversions_tb]

Checking bit1 functions

Bit1 as Y Address Bits PASSED

Bit1 as X Address Bits PASSED

Checking bit2 functions

Bit2 as Y Address Bits PASSED

Bit2 as X Address Bits PASSED

Checking bit1, bit2 logical combinations

Bit1 AND Bit2 PASSED

Bit1 OR Bit2 PASSED

Bit1 XOR Bit2 PASSED

Check X and Y parity

XYodd PASSED

XYEven PASSED

Xeven_Yodd PASSED

Xodd_Yeven PASSED

Xodd PASSED

Xeven PASSED

Yodd PASSED

Yeven PASSED

Check DTOPO inversions

DTopo RAM PASSED

Check Yindex Counter

YIndex Counter PASSED

Check Yindex Mask Inversions

yindex plus Y, yindex = 0xffff

yindex plus Y bar, yindex = 0xffff

yindex plus Y, Y = 0xffff

yindex plus Y bar, Y = 0x0000

YIndex Mask Inversions PASSED

Check XY Equality Functions

xmain equal to xbase (XEQB)

xmain less than xbase (XLTB)

xmain less than or equal to xbase (XLEB)

xmain equal to xfield or xbase (XEQBORF)

ymain equal to ybase (YEQB)

ymain less than ybase (YLTB)

ymain less than or equal to ybase (YLEB)

ymain equal to yfield or ybase (YEQBORF)

xymain equal to xybase (XYEQB)

xymain less than xybase (XYLTBXF)

xymain less than xybase (XYLTBYF)

xymain less than or equal to xybase (XYLEBXF)

xymain less than or equal to xybase (XYLEBYF)

inversion from uRAM (INVSNS)

inversion from uDATA (XORINV)

Testing ECR X Scramble RAM - short march [ecr_xscram_short_march_tb]

Testing ECR Y Scramble RAM - short march [ecr_yscram_short_march_tb]

Testing ECR Row RAM - short march [ecr_rowram_short_march_tb]

Testing ECR Col RAM - short march [ecr_colram_short_march_tb]

Testing ECR dimm bit independence [ecr_dimm_bit_independence_tb]

Testing ECR 5N March [ecr_dimm_hw_long_march_tb]

Testing DBM DRAM - short march [dbm_dimm_short_march_tb]

Testing DBM DIMM 5N March [dbm_dimm_hw_5N_march_tb]

Testing TG Pin Scramble RAM - short march [tg_psram_short_march_tb]

Testing TG timing RAM - short march [tg_timing_ram_short_march_tb]

Testing TG SLVM RAM - short march [tg_slvm_ram_short_march_tb]

Testing TG broadcast mode [tg_broadcast_tb]

Testing TG to PE communications [tg_pe_communication_tb]

Testing PE error generation [pe_error_gen_tb]

Testing PE force drive state [pe_force_drive_state_tb]

Testing PE force drive state [pe_vz_state_tb]

Testing strobe modes [pe_strobe_mode_tb]

Test Edge and Window modes single data rate mode

Test A and B cycle PES functions in dual data mode

Testing Pin Scramble Format RAM - short march [format_ram_short_march_tb]

Testing Pin Scramble RAM - short march [pe_psram_short_march_tb]

Testing DP ADC [adc_tb]

Testing DP PMU voltage force [pmu_vf_tb]

Testing DP 1 PMU voltage force DACs

Testing DP 1 PMU voltage force level accuracy

Testing DP 2 PMU voltage force DACs

Testing DP 2 PMU voltage force level accuracy

Testing DP 3 PMU voltage force DACs

Testing DP 3 PMU voltage force level accuracy

Testing DP 4 PMU voltage force DACs

Testing DP 4 PMU voltage force level accuracy

Testing DP PMU current force [pmu_if_tb]

Testing DP 1 PMU current force DACs

Testing DP 1 PMU current force level accuracy

Testing DP 2 PMU current force DACs

Testing DP 2 PMU current force level accuracy

Testing DP 3 PMU current force DACs

Testing DP 3 PMU current force level accuracy

Testing DP 4 PMU current force DACs

Testing DP 4 PMU current force level accuracy

Testing DP PMU voltage comparators [pmu_vcomp_tb]

Testing DP 1 PMU comparator DACs

Testing DP 2 PMU comparator DACs

Testing DP 3 PMU comparator DACs

Testing DP 4 PMU comparator DACs

Testing DP 1 PMU comparator accuracy

Testing DP 2 PMU comparator accuracy

Testing DP 3 PMU comparator accuracy

Testing DP 4 PMU comparator accuracy

Testing DP PMU voltage clamps [pmu_vclamp_tb]

Testing DP PMU current limit [pmu_ilimit_tb]

Testing DP PMU compensation capacitors [pmu_cap_tb]

Testing DP PMU/DPS current measure [range_resistor_tb]

Testing DPS voltage force [dps_vf_tb]

Testing DP DPSn DACs

Testing DP DPSn level accuracy

Testing DP DPSn apg level DAC select path

Testing DP DPSa DACs

Testing DP DPSa level accuracy

Testing DPS switches [dps_switch_tb]

Testing DPS current share [dps_ishare_tb]

Testing DPS sense resistor bypass diodes [dps_diode_tb]

Testing DPS compensation capacitors [dps_cap_tb]

Testing DPS leakage current [dps_leakage_tb]

Testing DPS current capability [dps_imin_tb]

Testing DP HV voltage force [hv_vf_tb]

Testing HV DACs

Testing HV level accuracy

Testing DP HV leakage current [hv_leakage_tb]

Testing DP HV current measure [hv_imeas_tb]

Testing PE leakage current [pe_leakage_tb]

Testing PE VIH pin level [vih_tb]

Testing VIH DACs

Testing VIH level accuracy

Testing VIH apg level DAC select path

Testing PE VIL pin level [vil_tb]

Testing VIL DACs

Testing VIL level accuracy

Testing VIL apg level DAC select path

Testing PE VIHH pin level [vihh_tb]

Testing VIHH DACs

Testing VIHH level accuracy

Testing VIHH apg level DAC select path

Testing PE VTT pin level [vtt_tb]

Testing VTT DACs

Testing PE VOH pin level [voh_tb]

Testing VOH DACs

Testing VOH level accuracy

Testing PE VOL pin level [vol_tb]

Testing VOL DACs

Testing VOL level accuracy

Testing PE VZ pin level [vz_tb]

Testing PE output impedance [pe_rout_tb]

Testing PE Verniers [vern_check_tb]

Testing PE XY Address SDR Pin Scramble [pe_ps_xy_tb]

Testing X Address bits

X Address 50.0MHz Test (20 ns)

Testing Y Address bits

Y Address 50.0MHz Test (20 ns)

Testing PE Data Pin Scramble [pe_ps_data_tb]

Testing Data bits

Data Bits 50.0MHz Test (20 ns)

Testing Data Strobes

Data Strobes 20.0MHz Test (50 ns)

Testing PE Chip Select Pin Scramble [pe_ps_cs_tb]

Testing Chip Selects

Chip Selects 50.0MHz Test (20 ns)

Testing Chip Select Strobes

Chip Select Strobes 4.0MHz Test (250 ns)

Testing PE Force Pin Scramble [pe_ps_force_tb]

Testing Drive L/H/Z

Drive Low 50.0MHz Test (20 ns)

Drive High 50.0MHz Test (20 ns)

Tri-State 50.0MHz Test (20 ns)

Testing Strobe L/H/V/M

Strobe Low 20.0MHz Test (50 ns)

Strobe High 20.0MHz Test (50 ns)

Strobe Valid 20.0MHz Test (50 ns)

Strobe Mid 20.0MHz Test (50 ns)

Testing PE LVM Pin Scramble [pe_ps_lvm_tb]

Testing Drive 0/1/X

Drive 0 50.0MHz Test (20 ns)

Drive 1 50.0MHz Test (20 ns)

Drive X 50.0MHz Test (20 ns) (HiZ)

Testing Strobe L/H/V/Z

Strobe L 20.0MHz Test (50 ns)

Strobe H 20.0MHz Test (50 ns)

Strobe V 20.0MHz Test (50 ns)

Strobe Z 20.0MHz Test (50 ns)

Testing PE XY Address DDR Pin Scramble [pe_ps_xy_ddr_tb]

Testing X Address bits

X Address 50.0MHz Test (20 ns)

Testing Y Address bits

Y Address 50.0MHz Test (20 ns)

Testing PE Data Pin Scramble [pe_ps_data_ddr_tb]

Testing Data bits

Data Bits 50.0MHz Test (20 ns)

Testing Data Strobes

Data Strobes 20.0MHz Test (50 ns)

Testing PE Chip Select Pin Scramble [pe_ps_cs_ddr_tb]

Testing Chip Selects

Chip Selects 50.0MHz Test (20 ns)

Testing Chip Select Strobes

Chip Select Strobes 4.0MHz Test (250 ns)

Testing PE Force Pin Scramble [pe_ps_force_ddr_tb]

Testing Drive L/H/Z

Drive Low 50.0MHz Test (20 ns)

Drive High 50.0MHz Test (20 ns)

Tri-State 50.0MHz Test (20 ns)

Testing Strobe L/H/V/M

Strobe Low 20.0MHz Test (50 ns)

Strobe High 20.0MHz Test (50 ns)

Strobe Valid 20.0MHz Test (50 ns)

Strobe Mid 20.0MHz Test (50 ns)

Testing PE LVM Pin Scramble [pe_ps_lvm_ddr_tb]

Testing Drive 0/1/X

Drive 0 50.0MHz Test (20 ns)

Drive 1 50.0MHz Test (20 ns)

Drive X 50.0MHz Test (20 ns) (HiZ)

Testing Strobe L/H/V/Z

Strobe L 20.0MHz Test (50 ns)

Strobe H 20.0MHz Test (50 ns)

Strobe V 20.0MHz Test (50 ns)

Strobe Z 20.0MHz Test (50 ns)

Testing TG->PE Timing Formats [pe_tg_format_tb]

Testing NRZ Format 5.0MHz Test (200 ns) with Edge Strobes

Testing NRZ Format 5.0MHz Test (200 ns) with Window Strobes

Testing RTO Format 5.0MHz Test (200 ns) with Edge Strobes

Testing RTO Format 5.0MHz Test (200 ns) with Window Strobes

Testing RTZ Format 5.0MHz Test (200 ns) with Edge Strobes

Testing RTZ Format 5.0MHz Test (200 ns) with Window Strobes

Testing TG->PE Timing Generators [pe_tg_dclk_format_tb]

Testing DCLKPOS Format 5.0MHz Test (200 ns) with Edge Strobes

Testing DCLKPOS Format 5.0MHz Test (200 ns) with Window Strobes

Testing DCLKNEG Format 5.0MHz Test (200 ns) with Edge Strobes

Testing DCLKNEG Format 5.0MHz Test (200 ns) with Window Strobes

Testing TG->PE Timing Generators [pe_tg_mux_mode_tb]

Testing MUX Mode 5.0MHz Test (200 ns) with Edge Strobes

Testing MUX Mode 5.0MHz Test (200 ns) with Window Strobes

Testing VMC FIFO Resident Loop counter branching [vmc_fifo_loop_branching_tb]

Running vmc_fifo_loop1_np_pat

PASS: vmc_fifo_loop1_np_pat

Running vmc_fifo_loop2_np_pat

PASS: vmc_fifo_loop2_np_pat

Running vmc_fifo_loop3_np_pat

PASS: vmc_fifo_loop3_np_pat

Running vmc_fifo_loop4_np_pat

PASS: vmc_fifo_loop4_np_pat

Running vmc_fifo_loop5_np_pat

PASS: vmc_fifo_loop5_np_pat

Running vmc_fifo_loop6_np_pat

PASS: vmc_fifo_loop6_np_pat

Testing VMC RAM Resident Loop counter branching [vmc_ram_loop_branching_tb]

Running vmc_ram_loop_np_pat

PASS: vmc_ram_loop_np_pat

Testing LVM Subroutine Branching [lvm_subroutines_tb]

Testing LVM Subroutine Branching DDR [lvm_subroutines_ddr_tb]

Testing Scan Functionality [scan_tb]

Standard Mode SCAN Tests - No Subs - No Strobes

Standard Mode SCAN Tests - No Subs - Strobe for Expect == Actual

Standard Mode SCAN Tests - Local Subs - Strobe for Expect == Actual

Standard Mode SCAN Tests - Remote Subs - Strobe for Expect == Actual

Standard Mode SCAN Tests - External Subs - Strobe for Expect == Actual

Standard Mode SCAN Tests - No Subs - Strobe for Expect != Actual

Standard Mode SCAN Tests - Local Subs - Strobe for Expect != Actual

Standard Mode SCAN Tests - Remote Subs - Strobe for Expect != Actual

Standard Mode SCAN Tests - External Subs - Strobe for Expect != Actual

Split Mode SCAN Tests - No Subs - No Strobes

Split Mode SCAN Tests - No Subs - Strobe for Expect == Actual

Split Mode SCAN Tests - Local Subs - Strobe for Expect == Actual

Split Mode SCAN Tests - Remote Subs - Strobe for Expect == Actual

Split Mode SCAN Tests - External Subs - Strobe for Expect == Actual

Split Mode SCAN Tests - No Subs - Strobe for Expect != Actual

Split Mode SCAN Tests - Local Subs - Strobe for Expect != Actual

Split Mode SCAN Tests - Remote Subs - Strobe for Expect != Actual

Split Mode SCAN Tests - External Subs - Strobe for Expect != Actual

TG Hold SCAN Tests - No Subs - Strobe for Expect == Actual

TG Hold SCAN Tests - No Subs - Strobe for Expect != Actual

Testing Scan DDR Functionality [scan_ddr_tb]